A memory capacity of a semiconductor memory represented by a Dynamic Random Access Memory (DRAM) has been increased year by year owing to a progress of micromachining technologies. It is actual circumstances that, the more the semiconductor device has become micro, the more the number of defective memory cells included per chip has been increased. Such defective memory cells are usually replaced by redundant memory cells, and an address having a defect is thus relieved.
In general, the address having a defect is stored in a fuse circuit including plural program fuses, and when an access to the address concerned is requested, an alternative access will be made by a control of the fuse circuit not to the defective memory cells but to the redundant memory cells.
With regard to a configuration of the fuse circuit, as described in Japanese Patent Laid-Open Nos. H9 (1997)-69299 and H6 (1994)-44795, there is known a system of storing a desired address by assigning a pair (two) of program fuses to each bit constituting an address to be stored and by cutting either one thereof. However, this system has a problem that it is necessary to prepare extremely many program fuses on a chip since two program fuses are required for each bit, resulting in an increase of a circuit area occupied by the fuse circuit.
Moreover, while the program fuse is usually cut by being irradiated with a laser beam, one program fuse must be cut for each bit without fail in the above-described system. Accordingly, the above-described system has a problem that the number of program fuses to be cut is relatively increased, and as a result, a time required for a step of cutting the fuses is lengthened and therefore manufacturing efficiency of the semiconductor device is reduced. Moreover, the above-described system also has a problem that a lifetime of a fuse cutting apparatus is shortened when the number of program fuses to be cut is large, leading to an increase in manufacturing cost of the semiconductor device. Furthermore, since a success rate of the cutting by the fuse cutting apparatus is not always 100%, another problem may also occur, in which an occurrence probability of a product failure owing to a cutting error is increased in response to the increase in the number of program fuses to be cut, leading to damage on reliability of the semiconductor device as an end product.
As opposed to this, as described in Japanese Patent Laid-Open No. H6 (1994)-119796, a system of assigning one program fuse to each of bits constituting the address to be stored is also known. In this system, a match or mismatch between a logical value stored in the program fuse and a logical value given by an access is detected by using an exclusive OR circuit (EXOR), an exclusive NOR circuit (EXNOR), and the like, and when the logical values match with each other in the entire bits (or mismatch with each other in the entire bits), a match (HIT) between the stored address and an address given by the access is detected.
As described above, according to the system described in Japanese Patent Laid-Open No. H6 (1994)-119796, it is made possible to reduce the number of program fuses to be cut to a large extent as compared with the systems described in Japanese Patent Laid-Open Nos. H9 (1997)-69299 and H6 (1994)-44795. However, it has not always been possible to reduce the number of program fuses to be cut to a large extent since the number of program fuses to be actually cut strongly depends on a bit configuration of the address to be stored.